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A customer sends an x-ray image of a BGA ball with a dark circle inside it and asks one question: is this a defect? The image on its own cannot answer it. Voiding in lead-free reflow is process-intrinsic - gas released by the flux that failed to leave the joint before the solder froze - and no convection reflow process drives it to zero. What decides whether a particular void is a defect is the class of void, the document your contract points at, and how much the measurement behind the number can be trusted. All three have moved in the last decade, and the percentage most engineers still quote comes from a revision that was superseded in 2014.
"This standard is a collection of visual quality acceptability requirements for electronic assemblies. This standard does not provide criteria for cross-section evaluation or x-ray inspection. There are x-ray guidelines located in J-STD-001." - IPC-A-610J, clause 1.1, March 2024
That sentence carries more weight than any threshold. The acceptability standard that purchase orders reference and operators are trained against states in its own scope clause that it does not judge radiographic images. The x-ray guidelines sit in IPC J-STD-001J (March 2024), in Appendix C, and the area array requirements there are split by ball type: clause 7.5.14.1 covers ball grid array components with collapsing balls, clause 7.5.14.2 those with noncollapsing balls. One percentage was never meant to cover both.
The document that discusses BGA voiding at length sends you back the other way:
"For accept/reject criteria and requirements for BGA assemblies, see IPC J-STD-001 and IPC-A-610." - IPC-7095E, clause 1.1.1, August 2024
Two documents, each pointing at the other, and neither handing you the simple number the question seems to demand. IPC-7095E also carries the word Guidance in its title, which is the status of everything it says about voiding.
The number people quote does have a history, and it belongs in the past tense:
The revision dates and the revision J scope wording were verified against IPC's published front matter. The 25 % and 30 % values come from trade summaries and from a 2005 NPL report written while 25 % was current, because the standards themselves are paywalled; the revision G treatment of noncollapsing balls we could not verify at all. Revision J does still carry a clause numbered 8.3.12.4, "Surface Mount Area Array - Voids", so the subject has not disappeared from the standard - but we have not read that clause, and you should not take our word for what is in it. If your contract names a revision, read that revision.
The structure of IPC-7095E shows what the industry actually does with void data. Clause 7.5 identifies and classifies voids. Clause 7.6 covers their measurement and opens with 7.6.1, "X-Ray Detection and Measurement Cautions". Clause 7.6.3 asks you to develop a void protocol, 7.6.4 to define a sampling plan for void evaluation. Clause 7.7 is about reducing voids through process control, and Appendix A is titled "Process Control Characterization to Reduce the Occurrence of Voids".
That is the anatomy of a document about holding a process steady, not one about sorting good boards from bad. A void percentage behaves like printed paste volume or reflow delta-T: you baseline it, you watch its distribution, and you investigate when it drifts. Promoting it to a pass/fail gate puts a control chart in a job it was never designed for.
Three statements get blurred in these discussions, and an engineer on the customer side separates them instantly: the standard requires, the industry commonly does, and this customer's specification demands. Only the third can turn a given void into a rejected board, and it does so because somebody wrote it into a document - not because solder behaves differently on one side of a round number.
IPC-7095E splits BGA voids into six types in clause 7.5.3: macrovoids, planar microvoids, shrinkage voids, microvia voids, intermetallic compound microvoids and pinhole voids. They differ in cause and they differ in consequence.
Macrovoids are the ones on your screen - gas from decomposing flux trapped in the ball. A Bosch study presented at IPC APEX EXPO 2018 describes voids as "gaseous inclusions within the solder joints containing organic substances" and shows, with in-situ x-ray during reflow, that bubbles form, grow and escape repeatedly while the solder is liquid. The void level during the melting phase runs "like an irregular saw tooth cycle", and what you inspect afterwards is whichever frame of that cycle happened to freeze.
Planar microvoids - champagne voids - behave differently. A MacDermid paper presented at IPC APEX EXPO 2007 defines them as inclusions of roughly 5 to 40 µm that "always occur at the interface of the bulk solder and the copper substrate", reports that high densities of them "do not affect assembly yields, but do present significant reliability risk", and attributes to them excessive crack propagation under temperature cycling. That paper comes from a supplier of board finishing chemistry, so weigh its process recommendations accordingly - but its physical description matches the Bosch work, which adds the inspection consequence: these voids "are not visible in standard 2D-X-ray analysis due to limited resolution".
Put those two paragraphs side by side and the practical answer surfaces. The voids you can measure are largely the tolerant class. The class with the clearest link to early cracking is the one your void percentage does not contain. A board that passed a 2D void check has been cleared of macrovoiding, not of interfacial voiding.
The National Physical Laboratory evaluated seven lead-free pastes from three manufacturers across a range of reflow profiles, then thermally cycled assemblies built at three deliberately different void levels. Its 2005 report states that no paste exhibited voids in any PBGA joint greater than 15 % despite attempts to provoke higher voiding, and that after 2000 cycles between -55 °C and +125 °C, "despite these samples having higher voiding levels than those stipulated for class 3 of the IPC's BGA Assembly and Inspection Guidelines, no adverse effect on reliability was seen". Shear strength degradation of chip resistors at those void levels was likewise unaffected.
Bosch ran the harder version of the experiment: BGA 416 packages with SAC balls and SAC paste, daisy-chained for live monitoring, with reflow parameters deliberately tuned for minimum and maximum voiding, cycled between -40 °C and +125 °C until testing stopped at 9000 cycles. Standard production settings gave average void levels of 1 to 3 %; the worst-case settings gave 11 to 18 %. The outcome was a slight but visible downward trend of cycles to failure against void level, on a regression that explained only a few percent of the scatter - R² of 0.06 against average voiding and 0.04 against maximum voiding. Across roughly 60 000 balls measured in that work, 99.7 % of balls came in below 10 % void area.
The same paper is honest about the direction of the published literature: "Positive as well as negative effects of voids on reliability, mainly depending on size and positions of voids within the ball, have been reported." The mechanism it offers for the positive half explains why the effect is so weak - a void softens its own ball, which lets that joint pass part of the strain to its neighbours instead of concentrating it. The standing reference for the negative half is Yunus, Srihari, Pitarresi and Primavera, Effect of voids on the reliability of BGA/CSP solder joints, Microelectronics Reliability 43 (2003), 2077-2086.
Two results from the Bosch work deserve to survive the summary, because they cut against the instinct to minimise voids at any cost. A high-reliability alloy, SnAg3.8Cu0.7Bi3.0Sb1.5Ni0.15, improved thermal cycling life by a factor of 1.5 to 2 over standard SAC while producing slightly more voiding; soft-terminated chip resistors showed the same pattern of more voids and longer life. A void limit written tightly enough can block the material change that would have bought real reliability, which is why the authors argue that void reduction should be examined for whether it improves solder joint reliability at all.
For the exposed pads that customers usually raise in the same breath as BGAs, their thermal resistance calculation for a 30 mm² pad with 25 thermal vias on a standard PCB shows overall Rth is insensitive to voiding up to around 80 % area, because the laminate rather than the solder is the bottleneck. That reverses on thick or massive copper such as DBC substrates, where the solder layer does govern heat flow and vacuum reflow starts to earn its cost. For a thermal pad the number that matters is the heat path, not the void percentage.
Two facts about 2D void measurement belong in every conversation that reaches a percentage.
The first is geometric. A transmission image measures projected area, not volume, and it does not tell you at what height in the ball the void sits - floating in the bulk, or pressed against the pad where it removes load-bearing interface. The MacDermid paper makes the same point about microvoids: with x-ray "there may be doubt as to whether a void exists within the bulk solder or at the copper interface". Oblique views help, which is why viewing angle is a real specification on an inspection system rather than a brochure line; our x-ray inspection system images at up to 70°, and cross-sectional techniques such as laminography and CT remove the ambiguity entirely at a cost in throughput.
The second is metrological, and it ends most disputes. Bosch measured the same BGA region under varying tube settings and found the reported void content changed by roughly a factor of 2 from the x-ray parameters alone, with image processing contributing an uncertainty of similar size - and no reproducible measurement reference exists to calibrate against. Their conclusion was that void measuring capability is, in the metrological sense, not given.
The consequence for a supply relationship is concrete. A number produced on your machine and a number produced on ours are not comparable unless the machine, the tube settings, the magnification and the image analysis threshold are fixed in the inspection instruction. Without that, the same board can pass at one plant and fail at another with no physical difference between them, and both sides will be certain the other is wrong.
Void counting is the least interesting thing a BGA x-ray does. The defects that cause field returns are the ones with no reading on a scale, and IPC-7095E defines the two hardest in clause 1.4:
Both usually pass electrical test at time zero and fail months later in the field. Both are difficult in straight-down 2D transmission, because a head-on-pillow joint projects as a ball of roughly normal diameter; the tell is a seam or a subtle density step, far easier to see at an angle. That is the honest limit of the method - x-ray lowers the risk of missing them, it does not eliminate it. Where the stake justifies destructive confirmation, the dye and pull test method IPC-TM-650 2.4.53, listed among the applicable documents of IPC-7095E (August 2024), shows the crack path no radiograph resolves.
Warpage, popcorning, bridging, misalignment and uneven heating across a large package are the other conditions where x-ray on an SMD assembly line changes decisions, and none of them reduces to a percentage either.
Four things belong in writing, ideally in the same document that carries your acceptance criteria.
Which document governs, by revision. "Per IPC" is not a specification. If you want a void limit, name it yourself and say which ball types it covers, because the current standards deliberately do not hand you one number.
Which void classes are evaluated, and how. Macrovoid area percentage from 2D transmission is one measurement; interfacial voiding is a different question that 2D imaging will not answer.
The measurement recipe. Machine, settings, magnification, analysis threshold and sampling plan - IPC-7095E devotes separate clauses to protocol development and to sampling because the answer depends on all of them.
What happens on exceedance. Rework of a BGA is itself a reliability event; a joint reballed and resoldered to remove an oversized void is not obviously better than the joint you started with. Deciding this in advance, with data, beats deciding it under schedule pressure.
Handled this way, the original question dissolves into a better one. Not is this void a defect, but is this process in control, and does this product's mission profile care. If you want that answered for a specific board rather than in general, send the Gerber files, the BOM and the mission profile with your request for a quote and say what the assembly has to survive.
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